Conventional dynamic random-access memory (DRAM) cells utilize capacitors to store data. It is desired to maintain the capacitance of such DRAM storage cell capacitors as the DRAM memories are shrunk to smaller dimensions in order to prevent increased leakage. In order to do so, high dielectric constant (high κ) materials may be used in the DRAM memory cell capacitor. This approach has not been able to maintain the capacitance of DRAM cells to lower sized nodes. Consequently, scaling of DRAM has been adversely affected.
Capacitors having a ferroelectric layer in the dielectric between the two electrodes are known. Most such conventional approaches focus on a capacitance matching condition between the ferroelectric layer and the remainder of the capacitor's dielectric. However, it is not clear from such approaches that the desired capacitance is realizable or that the capacitor will not suffer from degradation in performance for other reasons.
Accordingly, what is desired is an improved semiconductor memory device, such as a DRAM memory cell, that may be scalable to higher areal densities.